Make file tutorials




















This tutorial does not even scratch the surface of what is possible using make , but is intended as a starters guide so that you can quickly and easily create your own makefiles for small to medium-sized projects. Let's start off with the following three files, hellomake. This compiles the two. The -I. Unfortunately, this approach to compilation has two downfalls.

First, if you lose the compile command or switch computers you have to retype it from scratch, which is inefficient at best. Second, if you are only making changes to one. So, it's time to see what we can do with a makefile. If you put this rule into a file called Makefile or makefile and then type make on the command line it will execute the compile command as you have written it in the makefile.

Note that there is exactly one tab before the gcc command on the second line this is important in makefiles. Once this Makefile is written every time the user types make in the same directory as the Makefile make will check to see if source. Depending on the project you may want to introduce some variables to your make file.

Here is an example Makefile with variables present. Now lets explore what happened here. In the first line we declared a variable named CFLAGS that holds several common flags you may wish to pass to the compiler, note that you can store as many flags as you like in this variable.

Then we have the same line as before telling make to check source. This is the syntax for telling Make to expand the variable out to what you typed before. Make clean is another useful concept to learn about make files. Lets modify the Makefile from above. As you can see we simply added one more rule to our Makefile , and one additional variable that contains all of our targets. By typing make clean you tell the make program to run the clean rule and then make will run the rm command to delete all of your targets.

I hope this brief overview of using make helps you speed up your workflow, Makefiles can become very complex, but with these ideas you should be able to get started using make and have a better understanding of what is going on in other programmers Makefiles. A rule describes when and how certain files rule's targets are created. It can also serve to update a target file if any of the files required for its creation target's prerequisites are newer than the target.

The second rule is the default rule used by make to create a. There are numerous directives available in various forms. The make program on your system may not support all the directives.

So please check if your make supports the directives we are explaining here. GNU make supports these directives. The ifeq directive begins the conditional, and specifies the condition. It contains two arguments, separated by a comma and surrounded by parentheses.

Variable substitution is performed on both arguments and then they are compared. The lines of the makefile following the ifeq are obeyed if the two arguments match; otherwise they are ignored. The ifneq directive begins the conditional, and specifies the condition.

The lines of the makefile following the ifneq are obeyed if the two arguments do not match; otherwise they are ignored. The ifdef directive begins the conditional, and specifies the condition. It contains single argument. If the given argument is true then condition becomes true. The ifndef directive begins the conditional, and specifies the condition. If the given argument is false then condition becomes true. The else directive causes the following lines to be obeyed if the previous conditional failed.

In the example above this means the second alternative linking command is used whenever the first alternative is not used. It is optional to have an else in a conditional. The text-if-true may be any lines of text, to be considered as part of the makefile if the condition is true. If the condition is false, no text is used instead.

If the condition is true, text-if-true is used; otherwise, text-if-false is used. The text-if-false can be any number of lines of text.

The syntax of the conditional-directive is the same whether the conditional is simple or complex. There are four different directives that test various conditions. The include directive allows make to suspend reading the current makefile and read one or more other makefiles before continuing. The filenames can contain shell file name patterns.

Extra spaces are allowed and ignored at the beginning of the line, but a tab is not allowed. When the make processes an include directive, it suspends reading of the makefile and reads from each listed file in turn. Let's see how we can now build a C program without ever explicitly telling Make how to do the compililation:. Static pattern rules are another way to write less in a Makefile, but I'd say are more useful and a bit less "magic". Here's their syntax:. Whatever was matched is called the stem.

The stem is then substituted into the prereq-pattern , to generate the target's prereqs. A typical use case is to compile. Here's the manual way :.

While I introduce functions later on, I'll foreshadow what you can do with them. The filter function can be used in Static pattern rules to match the correct files.

In this example, I made up the. Double-Colon Rules are rarely used, but allow multiple rules to be defined for the same target. If these were single colons, a warning would be printed and only the second set of commands would run. Add an before a command to stop it from being printed You can also run make with -s to add an before each line.

Add -k when running make to continue running even in the face of errors. Helpful if you want to see all the errors of Make at once. Add a - before a command to suppress the error Add -i to make to have this happen for every command. The export directive takes a variable and makes it accessible to sub-make commands.

In this example, cooly is exported such that the makefile in subdir can use it. Note: export has the same syntax as sh, but they aren't related although similar in function. There's a nice list of options that can be run from make. Check out --dry-run , --touch , --old-file. You can have multiple targets to make, i.

Recursive definitions will give an infinite loop error.



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